The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body including a field effect transistor, whereby a source region and a drain region are formed in the semiconductor body to form said transistor, and on the semiconductor body a gate region is formed above a channel region situated between the source region and the drain region, said gate region being formed by providing the semiconductor body with an (electrically) insulating layer, which is provided with a stepped portion in the thickness, whereafter the surface of the semiconductor body is provided with a. conductive layer which is removed again by etching, whereby a portion of the conductive layer, which lies against the stepped portion and which forms part of the gate region, remains intact. The invention also relates to a transistor which can be manufactured by such a method. Such a method is particularly suitable for the manufacture of discrete field effect transistors operating at a high frequency and, as in the case of a LDMOST (Lateral Double diffused Metal Oxide Semiconductor Transistor) having a high breakdown voltage. Such discrete field effect transistors can be used in an amplifier or driver stage for TV transmitters operating at a supply voltage of, for example, 28 V.
A method of the type mentioned in the opening paragraph is disclosed in U.S. Pat. No. 3,846,822, published on May 11, 1974. In said document a description is given of a method of manufacturing a DMOS transistor, in which a semiconductor body is provided with an insulating layer having a stepped portion in the thickness, in this case two stepped portions on either side of a strip-shaped mesa formed in the insulating layer. This insulating layer is provided with a conductive tungsten layer, the major part of which is removed again by etching. Making use of the shadow of the strip-shaped mesa, a part of the tungsten layer which is situated against a side face of the mesa is deliberately left intact in this etching operation. Said part forms the gate region of the transistor to be formed. Subsequently, a source region and a drain region of the transistor are formed on either side of the mesa, which serves as a mask. In a similar manner, also a part of the channel region of the transistor, which is situated below the gate region, is provided with a higher doping concentration. Finally, the source, gate and drain regions are provided with electrical connections.
A drawback of the known method is that, notwithstanding the low (electric) resistance of the gate region, also at a very short length, the use of metals proves to be very objectionable in practice. A gate region of polycrystalline silicon does not have these drawbacks and, of itself, also yields better transistors. However, ii is difficult to provide such a gate region with a sufficiently low resistance.